View NCP81231_8962204.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2016 december, 2017 ? rev. 1 1 publication order number: NCP81231/d NCP81231 high resolution buck controller with full usb pd features and 100% duty operation the NCP81231 is a synchronous buck that is optimized for converting battery voltage or adaptor voltage into power supply rails required in notebook, tablet, and desktop systems, as well as many other consumer devices using usb pd standard and c?type cables. the NCP81231 is fully compliant to the usb power delivery specification when used in conjunction with a usb pd or c?type interface controller. NCP81231 is designed for applications requiring dynamically controlled slew rate limited output voltage. features ? wide input voltage range: from 4.5 v to 28 v ? dynamically programmed frequency from 150 khz to 1.2 mhz ? i 2 c interface ? real time power good indication ? controlled slew rate voltage transitioning ? feedback pin with internally programmed reference ? high resolution dac voltage ? two independent current sensing inputs ? support inductor dcr sensing ? over temperature protection ? adaptive non?overlap gate drivers ? filter capacitor switch control ? 100% duty cycle operation ? latched over?voltage and over?current protection ? dead battery power support ? 5 x 5 mm qfn32 package typical application ? notebooks, tablets, desktops ? gaming ? monitors, tvs, and set top boxes ? consumer electronics ? car chargers ? docking stations ? power banks www.onsemi.com qfn32 5x5, 0.5p case 485ce marking diagram NCP81231 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb?free package (note: microdot may be in either location) 32 1 ordering information device package shipping ? NCP81231mntxg qfn32 (pb?free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCP81231 www.onsemi.com 2 figure 1. typical application circuit (dcr) cs 1 cs 2 clind sda scl vdrv int i2c curret limit indicator interrupt v1 v2 hsg1 lsg1 csp1 fb vsw 1 bst 1 csn1 csp2 cfet1 comp pgnd1 agnd q1 q2 cb1 cp cc rc co2 q5 enable vcc dbin en pdrv c vcc c vdrv dbout co 1 rpu rpd r cs 1 r cs 2 r drv l1 current sense 1 current sense 2 csn2 v1 vout q6 vbus
NCP81231 www.onsemi.com 3 figure 2. typical application circuit (rsense) cs 1 cs 2 clind sda scl vdrv int i2c curret limit indicator interrupt v1 v2 hsg1 lsg1 csp1 fb vsw 1 bst 1 csn1 csp2 cfet1 comp pgnd1 agnd q1 q2 cb1 cp cc rc co2 q5 enable vcc dbin en pdrv c vcc c vdrv dbout co 1 rpu rpd r cs 1 r cs 2 r drv l1 current sense 1 current sense 2 csn2 v1 vout q6 vbus figure 3. pinout 17 18 19 20 21 22 23 24 15 14 13 12 11 10 9 16 nc nc csn2 csp2 fb cs2 pgnd2 pdrv en comp int sda scl agnd agnd cfet 1 2 3 4 5 6 7 8 hsg1 lsg1 csp1 csn1 v1 pgnd1 clind cs1 31 30 29 28 27 26 25 32 dbout vout vsw1 nc bst1 vdrv vcc dbin
NCP81231 www.onsemi.com 4 figure 4. block diagram startup input uvlo _ + _ + error ota co 2 bst1 hsg1 vsw1 lsg1 vdrv pgnd1 csn1 csp1 v1 + _ csp2 csn2 vcc vdrv cs1 cs 2 cs 1 cs 1 cs 2 cs 2 nc clind int sda scl limit registers status registers i2c interface digital configuration oscillator reference int interface vfb comp cc rc cp cs 2_int cs 2_int cs 1_int config vdrv cfet dbin current limiting circuit for dead battery config vfb pg thermal shutdown ts protection driver control logic iuvlob bg pg ts clind bg + ? clindp1 climp1 ? + en 0.8v en en ts bg value register adc csp1 cs 1_int cs 2_int analog mux agnd flag + ? clindp2 climp2 clind vcc en logic enpol en _mask ? + vfb pg _low pg _high ? + pg vfb pg_msk ov _ref ov pg/ ov/ logic ov _msk ? + co vdrv vdrv pdrv cfet pdrv q2 v1 + ? 4.0v vdrv_rdy + ? 4.0v vcc_rdy q1 v2 dbout v1 fb csp1 csn2 vfb pdrv cfet v1 cs 1_int cs 2_int buck control logic pwm pwm ov rbld rs1 rs2 vout r1 table 1. pin function description pin pin name description 1 hsg1 s1 gate drive. drives the s1 n?channel mosfet with a voltage equal to vdrv superimposed on the switch node voltage vsw1. 2 lsg1 drives the gate of the s2 n?channel mosfet between ground and vdrv. 3, 22 pgnd power ground for the low side mosfet drivers. connect these pins closely to the source of the bottom n?channel mosfets. 4 csn1 negative terminal of the current sense amplifier. 5 csp1 positive terminal of the current sense amplifier. 6 v1 input voltage of the converter 7 cs1 current sense amplifier output. cs1 will source a current that is proportional to the voltage across csp1/csn1. connect cs1 to a high impedance monitoring input. 8 clind open drain output to indicate that the cs1 or cs2 voltage has exceeded the i 2 c programmed limit. 9 sda i 2 c interface data line. 10 scl i 2 c interface clock line. 11 int interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and other i 2 c programmable functions. 12 cfet controlled drive of an external mosfet that connects a bulk output capacitor to the output of the power converter. necessary to adhere to low capacitance limits of the standard usb specifications for power prior to usb pd negotiation. 13, 14 agnd the ground pin for the analog circuitry. 15 comp output of the transconductance amplifier used for stability in closed loop operation.
NCP81231 www.onsemi.com 5 table 1. pin function description (continued) pin description pin name 16 en precision enable starts the part and places it into default configuration when toggled. 17 pdrv the open drain output used to control a pmosfet or connect to an external resistor. 18 cs2 current sense amplifier output. cs2 will source a current that is proportional to the voltage across csp1/csn1. connect cs2 to a high impedance monitoring input. 19 fb feedback voltage of the output, negative terminal of the gm amplifier. 20 csn2 negative terminal of the current sense amplifier. used for dcr sensing. 21 csp2 positive terminal of the current sense amplifier. used for dcr sensing. 23?25 nc no connection. 26 vout connect to the buck output voltage. 27 dbout the output of the dead battery circuit which can also be used for the vconn voltage supply. 28 dbin the dead battery input to the converter where 5 v is applied. a 1 f capacitor should be placed close to the part to decouple this line. 29 vdrv internal voltage supply to the driver circuits. a 1 f capacitor should be placed close to the part to decouple this line. 30 vcc the vcc pin supplies power to the internal circuitry. the vcc is the output of a linear regulator which is powered from v1. can be used to supply up to a 100 ma load. pin should be decoupled with a 1 f capacitor for stable operation. 31 vsw1 switch node. vsw1 pin swings from a diode voltage drop below ground up to v1. 32 bst1 driver supply. the bst1 pin swings from a diode voltage below vdrv up to a diode voltage below v1 + vdrv. place a 0.1 f capacitor from this pin to vsw1. 33 thpad center pad, recommended to connect to agnd. table 2. maximum ratings (over operating free?air temperature range unless otherwise noted) rating symbol min max unit input of the dead battery circuit dbin ?0.3 5.5 v output of the dead battery circuit dbout ?0.3 5.5 v driver input voltage vdrv ?0.3 5.5 v internal regulator output vcc ?0.3 5.5 v output of current sense amplifiers cs1, cs2 ?0.3 3.0 v current limit indicator clind ?0.3 vcc + 0.3 v interrupt indicator int ?0.3 vcc + 0.3 v enable input en ?0.3 5.5 v i 2 c communication lines sda, scl ?0.3 vcc + 0.3 v compensation output comp ?0.3 vcc + 0.3 v v1 power stage input voltage v1 ?0.3 32 v, 40 v (20 ns) v positive current sense csp1 ?0.3 32 v, 40 v (20 ns) v negative current sense csn1 ?0.3 32 v, 40 v (20 ns) v positive current sense csp2 ?0.3 32 v, 40 v (20 ns) v negative current sense csn2 ?0.3 32 v, 40 v (20 ns) v feedback voltage fb ?0.3 5.5 v cfet driver cfet ?0.3 vcc + 0.3 v driver positive rail bst1 ?0.3 v wrt/pgnd ?0.3 v wrt/vsw 37 v, 40 v (20 ns) wrt/pgnd 5.5 v wrt/vsw v
NCP81231 www.onsemi.com 6 table 2. maximum ratings (continued) (over operating free?air temperature range unless otherwise noted) rating unit max min symbol high side driver hsg1 ?0.3 v wrt/pgnd ?0.3 v wrt/vsw 37 v, 40 v (20 ns) wrt/gnd 5.5 v wrt/vsw v switching node and return path of driver vsw1 ?5.0 v 32 v, 40 v (20 ns) v low side driver lsg1 ?0.3 v 5.5 v pmosfet driver pdrv ?0.3 40 v voltage differential agnd to pgnd ?0.3 0.3 v csp1?csn1, csp2?csn2 differential voltage cs1dif, cs2dif ?0.5 0.5 v pdrv maximum current pdrvi 0 10 ma pdrv maximum pulse current (100 ms on time, with > 1 s interval) pdrvipul 0 200 ma maximum vcc current vcci 0 80 ma operating junction temperature range (note 1) tj ?40 150 c operating ambient temperature range ta ?40 100 c storage temperature range tstg ?55 150 c thermal characteristics (note 2) qfn 32 5mm x 5mm maximum power dissipation @ ta = 25 c thermal resistance junction?to?air with solder pd r ja 4.1 30 w c/w lead temperature soldering (10 sec): reflow (smd styles only) pb?free (note 3) rf 260 peak c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the maximum package power dissipation limit must not be exceeded. 2. the value of ja is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch fr?4 board with 1.5 oz. copper on the top and bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with t a = 25 c. 3. 60?180 seconds minimum above 237 c. table 3. electrical characteristics (v1 = 12 v, v out = 5.0 v , t a = +25 c for typical value; ?40 c < t a < 100 c for min/max values unless noted otherwise) parameter symbol test conditions min typ max units power supply v1 operating input voltage v1 4.5 28 v vdrv operating input voltage vdrv 4.5 5 5.5 v vcc uvlo rising threshold vcc start 4.26 v uvlo hysteresis for vcc vccv hys falling hysteresis 320 mv vdrv uvlo rising threshold vdrv start 4.27 v uvlo hysteresis for vdrv vdrv hys falling hysteresis 340 mv vcc output voltage vcc with no external load 4.96 5 v vcc drop out voltage vccdroop 30 ma load 160 mv vcc output current limit iout vcc vcc loaded to 4.3 v 80 97 ma v1 shutdown supply current ivcc_sd en = 0 v, 4.2 v v1 28 v 6.7 7.7 ma vdrive switching current buck iv1_sw en = 5 v, cgate = 2.2 nf, vsw = 0 v, fsw = 600 khz 15 ma
NCP81231 www.onsemi.com 7 table 3. electrical characteristics (continued) (v1 = 12 v, v out = 5.0 v , t a = +25 c for typical value; ?40 c < t a < 100 c for min/max values unless noted otherwise) parameter units max typ min test conditions symbol voltage output voltage output accuracy vfb dac_target = 00110010 dac_target = 01111000 dac_target = 11001000 0.495 1.188 1.98 0.5 1.2 2.0 0.505 1.212 2.02 v voltage accuracy over temperature voutert ?40 c < t a < 100 c vfb > 0.5 v vfb < 0.5 v ?1.0 ?5 1.0 5 % mv vouter t a = 25 c vfb > 0.5 v ?0.45 0.45 % transconductance amplifier gain bandwidth product gbw 3 db (note 4) 5.2 mhz transconductance gm1 default 500 s max output source current limit gmsoc 60 83 a max output sink current limit gmsic 60 84 a voltage ramp vramp 1.4 v internal bst diode forward voltage drop vfbot i f = 10 ma, t a = 25 c 0.35 0.46 0.55 v reverse?bias leakage current dil bst?vsw = 5 v v sw = 28 v, t a = 25 c 0.05 1 a bst?vsw uvlo bst1 _uvlo rising (note 4) 3.5 v bst?vsw hysteresis bst _hys (note 4) 300 mv oscillator oscillator frequency fsw_0 fsw = 000, default 528 600 672 khz fsw_1 fsw = 001 132 150 168 khz fsw_7 fsw = 110 1056 1200 1344 khz oscillator frequency accuracy fswe ?12 12 % minimum on time mot measured at 10% to 90% of vcc, ?40 c < t a < 100 c 50 ns minimum off time moft measured at 90% to 10% of vcc, ?40 c < t a < 100 c 90 ns int thresholds interrupt low voltage vinti iint(sink) = 2 ma 0.2 v interrupt high leakage current inii 3.3 v 3 100 na interrupt startup delay intpg soft start end to pg positive edge 2.1 ms interrupt propagation delay pgi delay for power good in 3.3 ms pgo delay for power good out 100 ns power good threshold pgth power good in from high 105 % pgth power good in from low 95 % pgthys pg falling hysteresis 2.5 % fb overvoltage threshold fb_ov 140 % overvoltage propagation delay vfb_ovdl 1 cycle 4. ensured by design. not production tested.
NCP81231 www.onsemi.com 8 table 3. electrical characteristics (continued) (v1 = 12 v, v out = 5.0 v , t a = +25 c for typical value; ?40 c < t a < 100 c for min/max values unless noted otherwise) parameter units max typ min test conditions symbol external current sense (cs1,cs2) positive current measurement high cs10 csp1?csn1 or csp2?csn2 = 100 mv 500 a transconductance gain factor csgt current sense transconductance vsense = 1 mv to 100 mv 5 ms transconductance deviation csge ?20 20 % current sense common mode range cscmmr 3 28 v ?3db small signal bandwidth csbw vsense (ac) = 10 mvpp, rgain = 10 k (note 4) 30 mhz input sense voltage full scale isvfs 100 mv cs output voltage range csor vsense = 100 mv rset = 6k 0 3 v external current limit (clind) current limit indicator output low clindl input current = 500 a 10 100 mv current limit indicator output high clindh input current = 500 a 4.0 5.0 v internal current sense internal current sense gain for pwm icg cspx?csnx = 100 mv 9.2 9.9 10.5 v/v positive peak current limit trip ppclt int_cl = 00 34 39 44 mv negative valley current limit trip nvclt int_cl_neg = 00 31 40 45 mv switching mosfet drivers hsg pullup resistance hsg_pu bst?vsw = 4.5 v 2.9 hsg pulldown resistance hsg_pd bst?vsw = 4.5 v 1.1 lsg pullup resistance lsg_pu lsg ?pgnd = 2.5 v 3.4 lsg pulldown resistance lsg_pd lsg ?pgnd = 2.5 v 1.1 hsg falling to lsg rising delay hslsd 15 ns lsg falling to hsg rising delay lshsd 15 ns cfet cfet drive voltage cfetdv vcc v source/sink current cfetss cfet clamped to 2 v 2 a pull down delay cfetd measured at 10% to 90% of vcc, ?40 c < t a < 100 c 10 ms cfet pull down resistance cfetr measured with 1 ma pull up cur- rent, after 10 ms rising edge delay 1.3 k slew rate/soft start charge slew rate slewp slew = 00, fb = 0.1 vout slew = 11, fb = 0.1 vout 0.6 4.8 mv/ s discharge slew rate slewn slew = 00, fb = 0.1 vout slew = 11, fb = 0.1 vout ?0.6 ?4.8 mv/ s dead battery/vconn dead battery input voltage range vdb 4.5 5 5.25 v dead battery output voltage vio vdb = 5 v, ?40 c < t a < 100 c, output current 32 ma 4 4.7 5 v dead battery current limit db_lim vdb = 5 v, v1 greater than 2 v 29 57 ma 4. ensured by design. not production tested.
NCP81231 www.onsemi.com 9 table 3. electrical characteristics (continued) (v1 = 12 v, v out = 5.0 v , t a = +25 c for typical value; ?40 c < t a < 100 c for min/max values unless noted otherwise) parameter units max typ min test conditions symbol enable en high threshold voltage enht em_mask = enpu = enpol = 0 800 820 mv en low threshold voltage enlt 640 667 mv en pull up current ien_up en = 0 v 5 a en pull down current ien_dn en = vcc 5 a i 2 c interface voltage threshold i2cvth 0.95 1 1.05 v propagation delay i2cpd (note 4) 25 ns communication speed i2csp (note 4) 1 mhz internal adc range adcrn 0 2.55 v lsb value adclsb (note 4) 20 mv error adcfe (note 4) 1 lsb thermal shutdown thermal shutdown threshold tsd (note 4) 151 c thermal shutdown hysteresis tsdhys (note 4) 28 c pdrv pdrv operating range 0 28 v pdrv leakage current pdrv_ids fet off, vpdrv = 28 v 480 na pdrv saturation voltage pdrv_vds isnk = 10 ma 0.20 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. ensured by design. not production tested.
NCP81231 www.onsemi.com 10 application information feedback and output voltage profile the feedback of the converter output voltage is connected to the fb pin of the device through a resistor divider. internally fb is connected to the inverting input of the internal transconductance error amplifier. the non?inverting input of the gm amplifier is connected to the internal reference. the internal reference voltage is by default 0.5 v. therefore, for example, a 10:1 resistor divider from the converter output to the fb will set the output voltage to 5 v in default. the reference voltage can be adjusted with 10 mv(default) or 5 mv steps from 0.3 v to 2.55 v through the voltage profile register (01h), which makes the continuous output voltage profile possible through an external resistor divider. for example, if the external resistor divider has a 10:1 ratio, the output voltage profile will be able to vary from 3 v to 25.5 v with 100 mv steps but not above v1 voltage. table 4. voltage profile settings dac_taget dac_target_lsb voltage profile hex value reference voltage (mv) bit_8 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 0 0 0 0 0 0 0 0 0 00h reserved 0 0 0 0 1 0 0 0 1 00h reserved 0 0 0 0 0 0 0 1 0 01h reserved ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 1 1 0 1 1 1dh reserved 0 0 0 1 1 1 1 0 0 1eh 300 0 0 0 1 1 1 1 0 1 1eh 305 ? ? ? ? ? ? ? ? ? ? ? 0 0 1 1 0 0 1 0 0 32h 500 (default) ? ? ? ? ? ? ? ? ? ? ? 1 1 0 0 1 0 0 0 0 c8h 2000 ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 0 ffh 2550 1 1 1 1 1 1 1 1 1 ffh 2555 transconductance voltage error amplifier to maintain loop stability under a large change in capacitance, the NCP81231 can change the gm of the internal transconductance error amplifier from 87 s to 1000 s allowing the dc gain of the system to be increased more than a decade triggered by the adding and removal of the bulk capacitance or in response to another user input. the default transconductance is 500 s. table 5. available transconductance setting amp_2 amp_1 amp_0 amplifier gm value ( s) 0 0 0 87 0 0 1 100 0 1 0 117 0 1 1 333 1 0 0 400 1 0 1 500 1 1 0 667 1 1 1 1000
NCP81231 www.onsemi.com 11 programmable slew rate the slew rate of the NCP81231 is controlled via the i 2 c registers with the default slew rate set to 0.6 mv/ s (fb = 0.1 vout, assume the resistor divider ratio is 10:1) which is the slowest allowable rate change. the slew rate is used when the output voltage starts from 0 v to a user selected profile level, changing from one profile to another, or when the output voltage is dynamically changed. the output voltage is divided by a factor of the external resistor divider and connected to fb pin. the 9 bit dac is used to increase the reference voltage in 10 or 5 mv increments. the slew rate is decreased by using a slower clock that results in a longer time between voltage steps, and conversely increases by using a faster clock. the step monotonicity depends on the bandwidth of the converter where a low bandwidth wi ll result in a slower slew rate than the selected value. the available slew rates are shown in table 6. the selected slew rate is maintained unless the current limit is tripped, in which case the increased voltage will be governed by the positive current limit until the output voltage falls or the fault is cleared. figure 5. slew rate limiting block diagram and waveforms 9 bit dac + ? vout fb = 0.1*v2 dac_target cc rc dac_target_lsb vref 2.56 v ci comp table 6. slew rate selection slew bits soft start or voltage transition (fb = 0.1*vout) slew_0 0.61 mv/ s slew_1 1.2 mv/ s slew_2 2.4 mv/ s slew_3 4.9 mv/ s the discharge slew rate is accomplished in much the same way as the charging except the reference voltage is decreased rather than increased. soft start during a 0 v soft start, standard converters can start in synchronous mode and have a monotonic rising of output voltage. if a prebias exists on the output and the converter starts in synchronous mode, the prebias voltage will be discharged. the NCP81231 controller ensures that if a prebias is detected, the soft start is completed in a non?synchronous mode to prevent the output from discharging. frequency programming the switching frequency of the NCP81231 can be programmed from 150 khz to 1.2 mhz via the i 2 c interface. the default switching frequency is set to 600 khz. once the part is enabled, the frequency is set and cannot be changed while the part remains enabled. the part must be disabled with no switching prior to writing the frequency bits into the appropriate i 2 c register. table 7. frequency programming table name bit definition description freq1 03h [2:0] frequency setting 3 bits that control the switching frequency from 150 khz to 1 mhz. 000: 600 khz 001: 150 khz 010: 300 khz 011: 450 khz 100: 750 khz 101: 900 khz 110: 1.2 mhz 111: reserved
NCP81231 www.onsemi.com 12 100% duty cycle operation NCP81231 can operate in a 100% duty cycle mode when the high side switch works as a bypass switch. a detection circuit will constantly monitor the high side gate voltage and turn on low side switch to refresh the boost capacitor when the voltage across the boost capacitor is below the boost uvlo voltage. if the system stays in the 100% duty cycle operation, the output will always follow the input regardless the comp voltage and comp is likely to creep up. if a fast comp recovery is required, the following clamping circuitry can be considered with a lar ger than 1.5 v clamping voltage set as the target. figure 6. external comp clamping circuit r2 r1 comp vcc d1 NCP81231 current sense amplifiers internal differential amplifiers measure the potential between the terminal csp1/csn1 or csp2/csn2. the potential difference between cspx and csnx is level shifted from the high voltage domain to the low voltage vcc domain. both current sense signals can be monitored externally by cs1 and cs2 pins. they are fixed gm amplifier outputs, allowing users to set output gain by shunting resistors. cs1 correlates to the csp1/csn1 reading, cs2 correlates to the csp2/csn2 reading. when not used, csp1/csn pin can be shorted therefore cs1 reading is omitted. NCP81231 also uses csp2/csn2 current sense signal for current mode modulation and cycle by cycle positive and negative peak current limiting. the inputs of csp2/csn2 can be a current sense resistor or configured for inductor dcr sensing shown as figure 7. a resistor rs1 connects from switch node to csp2 and rs2 connects from the output voltage to csn2 respectively. two capacitors, cs1 and cs2, are common mode filtering capacitors from csp2 and csn2 to the ground. choose rs1=rs2=rs, cs1=cs2=cs; in order to replicate inductor current sensing information, rs*cs needs to be equal or slightly higher than the ratio of output inductance over its dc resistance or l/dcr. additional resistor network may be added to expand the actual current limit tripping range. figure 7. block diagram for current sense channel r cs + ? + ? + ? + ? csn1/csn2 csp1/csp2 c cs cs2 clind vcm + ? 10x + ? + ? positive current limit negative current limit clip clin vcc internal path cs1 or cs2 adc r cs c cs cs1 + ? + ? cs2 mux cs1 mux 2 2 ramp 1 ramp 2 10x(csp2-csn2) 10x(csp2-csn2)
NCP81231 www.onsemi.com 13 figure 8. inductor dcr sensing using csp2/csn2 l dcr rs 1 cs1 csp2 csn2 s1 s2 rs2 cs2 vout swn positive current limit internal path the NCP81231 has a pulse by pulse current limiting function activated when a positive current limit triggers. when a positive current limit is triggered, the current pulse is truncated. for NCP81231, the csp2/csn2 pins will be the positive current limit sense channel. the s1 switch is turned off to limit the energy during an over current event. the current limit is reset every switching cycle and waits for the next positive current limit trigger. in this way, current is limited on a pulse by pulse basis. pulse by pulse current limiting is advantageous for limiting energy into a load in over current situations but are not up to the task of limiting energy into a low impedance short. to address the low impedance short, the NCP81231 will go to latch up mode if pulse by pulse current limiting continues for more than 4 cycles. toggling the enable pin or resetting the input voltage (v1) will clear the latched ocp fault. table 8. internal peak current limit clip_1 clip_0 clim delta value (mv) csp2?csn2 (mv) trip current inductor dcr = 2 m (a) 0 0 380 38 19 0 1 230 23 11.5 1 0 110 11 5.5 1 1 700 70 35 external path (cs1, cs2, clind) the voltage drop across csp1/csn1 or csp2/csn2 as a result of the load can be observed on the cs1 and cs2 pins. the voltage drop is converted into a current by a transconductance amplifier with a typical gm of 5 ms. the final gain of the output is determined by the end users selection of the r cs resistors or the inductor dcr resistor. the output voltage of the cs pin can be calculated from equation 1. the user must be careful to keep the dynamic range below 3.0 v when considering the maximum short circuit current. v cs (i load_max *r sense * trans) * r cs (eq. 1) 2.967 v (8.5 a * 5 m * 5 ms) * 13.96 k r cs v cs i load *r sense * trans 13.96 k 2.967 v 8.5 a * 5 m *5ms the speed and accuracy of the dual amplifier stage allows the reconstruction of the input and output current signal, creating the ability to limit the peak current. if the user would like to limit the mean dc current of the switch, a capacitor can be placed in parallel with the r cs resistors. the external cs voltages are connected to 2 high speed low offset comparators. the comparators output can be used to suspend operation until reset or restart of the part depending on i 2 c configuration. when one of the comparators trips if not masked, the external clind flag is triggered to indicate that the internal comparator has exceeded the p reset limit. the default comparator setting is 250 mv which is a limit of 500 ma with a current sense resistor of 5 m and an r cs resistor of 20 k . the block diagram in figure 9 shows the programmable comparators and the settings are shown in table 9.
NCP81231 www.onsemi.com 14 figure 9. block diagram for clim comparator clim mux cs1 clind cs2 cs1 bg resistor network r cs2 r cs2 cs2 mux cs1_lim ? + buffer ? + mux buffer cs1 cs2 cs2_lim table 9. register setting for the clim comparators climx_1 climx_0 csx_lim (v) current at rsense = 5 m rset = 20 k (a) current at rsense = 5 m rset = 10 k (a) 0 0 0.25 .5 1 0 1 0.75 1.5 3 1 0 1.5 3 6 1 1 2.5 5 10 overvoltage protection (ovp) when the d ivided output voltage is 140% (typical) above the internal reference voltage, a latched ov fault will be triggered. at 0 v reference voltage, it?s easy to trigger ovp falsely. so one should avoid using output voltage profile under 0.3 v for safety in normal operation. when 0 v output voltage is needed, one can disable NCP81231 by pulling en pin down, instead of setting output voltage profile to 0 via i2c. toggling the enable pin will not clear the latched ovp fault. only resetting the input voltage (v1) can clear it. power good monitor (pg) NCP81231 provides two window comparators to monitor the internal feedback voltage. the target voltage window is 5% of the reference voltage (typical). once the feedback voltage is within the power good window, a power good indication is asserted once a 3.3 ms timer has expired. if the feedback voltage falls outside a 7% window for greater than 1 switching cycle, the power good register is reset. power good is indicated on the int pin if the related i 2 c register is set to display the pg state. during startup, int is set until the feedback voltage is within the specified range for 3.3 ms. figure 10. pg block diagram ? + vfb pg_low pg_high ? + pg pg_msk table 10. power good masking pg_msk description 0 pg action and indication unmasked 1 pg action and indication masked thermal shutdown the NCP81231 protects itself from overheating with an internal thermal shutdown circuit. if the junction temperature exceeds the thermal shutdown threshold (typically 150 c), all mosfets will be driven to the off state, and the part will wait until the temperature decreases to an acceptable level. the fault will be reported to the fault register and the int flag will be set unless it is masked. when the junction temperature drops below 125 c (typical), the part will discharge the output voltage to 0 v.
NCP81231 www.onsemi.com 15 cfet turn on the cfet is used to engage the output bulk capacitance after successful negotiations between a consumer and a provider. the usb power delivery specification requires that no more than 30 f of capacitance be present on the vbus rail when sinking power. once the consumer and provider have completed a power role swap, a larger capacitance can be added to the output rail to accommodate a higher power level. the bulk capacitance must be added in such a way as to minimize current draw and reduce the voltage perturbation of the bus voltage. the NCP81231 incorporates a right drive circuit that regulates current into the gate of the mosfet such that the mosfet turns on slowly reducing the drain to source resistance gradually. once the transition from high to low has occurred in a controlled way, a strong pulldown driver is used to ensure normal operation does not turn on the power n?mosfet engaging the bulk capacitance. the cfet must be activated through the i 2 c interface where it can be engaged and disengaged. the default state is to have the cfet disengaged. figure 11. cfet drive cfet 30 f c bulk 10 h vcc 2 a 2 a cfet 10 ms rising edege delay lsg2 hsg2 q cfet vbus table 11. cfet activation table cfet_0 description 0 cfet drive pulldown 1 cfet drive pull up pfet drive the pmos drive is an open drain output used to control the turn on and turn off of pmosfet switches at a floating potential or to create an external discharging path. the rdson of the pulldown nmosfet is typically 20 allowing the user to quickly turn on for a fast output discharge or to control the external pass fets. table 12. pfet activation table pfet_drv description 0 nfet off (default) 1 nfet on figure 12. pfet drive pdrv pfet_drv vbus
NCP81231 www.onsemi.com 16 analog to digital converter the analog to digital converter is a 7?bit a/d which can be used as an event recorder, an input voltage sampler, output voltage sampler, input current sampler, or output current sampler. the converter digitizes real time data during the sample period. the internal precision reference is used to provide the full range voltage; in the case of input voltage v1 or the feedback voltage fb (with 10:1 external resistor divider) the full range is 0 v to 25.5 v. v1 is internally divided down by 10 before it is digitized by the adc, thus the range of the measurement is 0 v?2.55 v, same as fb. the resolution of the v1 and fb voltage is 20 mv at the analog mux, but since the voltage is divided by 10 output voltage resolution will be 200 mv. when cs1 and cs2 are sampled, the range is 0 v?2.55 v. the resolution will be 20 mv in the cs monitoring case. the actual current can be calculated by dividing the cs1 or cs2 values with the factor of rsense*5ms*rcsx, the total gain from the current input to the external current monitoring outputs. figure 13. analog to digital converter table 13. adc byte msb 5 4 3 2 1 lsb data d6 d5 d4 d3 d2 d1 d0 table 14. register setting for enabling desired adc behaviour adc_2 adc_1 adc_0 description 0 0 0 sets amux to vfb 0 0 1 sets amux to v1 0 1 0 sets amux to cs2 0 1 1 sets amux to cs1 1 0 0 select all in rotating sequence (vfb, v1, cs2, cs1, vfb, ? )
NCP81231 www.onsemi.com 17 interrupt control the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected. individual bits generating interrupts will be set to 1 in the int ack register (i 2 c read only registers), indicating the interrupt source. all interrupt sources can be masked by writing 1 in register intmsk. masked sources will never generate an interrupt request on the int pin. the int pin is an open drain output. a non?masked interrupt request will result in the int pin being driven high. figure 14 illustrates the interrupt process. figure 14. interrupt logic ov ov_mask temp temp_mask pg pg _mask intocp intocp_mask extoc extoc_mask intack intack_mask vchn vchn_mask shutdn shutdn_mask int ov pg temp int temp_reg ov _reg pg_reg table 15. interpretation table interrupt name description ov output over voltage shutdown shutdown detection (en=low) temp ic thermal trip pg power good trip thresholds exceeded intocp internal current limit trip extoc external current trip from clind vchn output negative voltage change intack i2c ack signal to the host i 2 c address NCP81231 has two address selectable factory settings. the default address is set to 77h. table 16. i 2 c address i 2 c address hex a6 a5 a4 a3 a2 a1 a0 add0 (default) 0x77 1 1 1 0 1 1 1 add1 0x76 1 1 1 0 1 1 0
NCP81231 www.onsemi.com 18 i 2 c interface the i 2 c interface can support 5 v ttl, l vttl, 2.5 v and 1.8 v interfaces with two precision scl and sda comparators with 1v thresholds shown in figure 15. the part cannot support 5 v cmos levels as there can be some ambiguity in voltage levels. i 2 c compatible interface the NCP81231 can support a subset of i 2 c protocol as detailed below. the NCP81231 communicates with the external processor by means of a serial link using a 400 khz up to 1.2 mhz i 2 c two?wire interface protocol. the i 2 c interface provided is fully compatible with the standard, fast, and high?speed i 2 c modes. the NCP81231 is not intended to operate as a master controller; it is under the control of the main controller (master device), which controls the clock (pin scl) and the read or write operations through sda. the i 2 c bus is an addressable interface (7?bit addressing only) featuring two read/write addresses. v ol =0.5v v il = 0.3*vcc v th = 0.5* vcc v ih = 0.7*vcc v oh =4.44v 5v cmos vcc =4.5v?5.5v vth = 1. 5v ttl vcc =4.5v? 5.5v v ol =0.4v v il =0.8v v ih =2.0v v oh =2.4v lvttl vcc =2.7v? 3.6v eis/jedec 8?5 v ol =0.4v v il =0.8v v ih =2.0v v oh =2.4v 1.8v vcc =1 .65v?1.95v eis/jedec 8? 7 v ol =0.45v v il = 0.35*vcc v ih = 0. 65*vcc v oh = vcc?0.45v 2. 5 vcc = 2.3 v?2. 7v eis/jedec 8?5 v ol =0.4v v il =0.7v v ih =1.7v v oh =2.0v 1.0v threshold figure 15. i 2 c thresholds and comparator thresholds i 2 c communication description the first byte transmitted is the chip address (with the lsb bit set to 1 for a read operation, or set to 0 for a write operation). following the 1 or 0, the data will be: ? in case of a write operation, the register address (@reg) pointing to the register for which it will be written is followed by the data that will written in that location. the writing process is auto?incremental, so the first data will be written in @reg, the contents of @reg are incremented, and the next data byte is placed in the location pointed to @reg + 1 .. ., etc. ? in case of a read operation, the NCP81231 will output the data from the last register that has been accessed by the last write operation. like the writing process, the reading process is auto?incremental. from mcu to NCP81231 start ic address 1 ack data 1 ack data n /ack stop read out from part from NCP81231 to mcu 1 read start ic address 0 ack data 1 ack data n stop write inside part 0 write /ack ack if part does not acknowledge, the /nack will be followed by a stop or sr. if part acknowledges, the ack can be followed by another data or stop or sr. figure 16. general protocol description
NCP81231 www.onsemi.com 19 read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction was pointed to: from mcu to NCP81231 start ic address 0 ack register address ack stop from NCP81231 to mcu start ic address 1 ack data 1 ack data n stop write inside part 0 read /ack sets internal register pointer 0 write register address value n register read register address + (n+1) value figure 17. read out from part from mcu to NCP81231 start ic address 0 ack register reg0 address ack stop from NCP81231 to mcu start ic address 1 ack data 1 ack data n stop 0 read /ack sets internal register pointer 0 write register address + (n? 1) value k register read register address +(n+1)+ (k? 1) value reg value write value in register reg0 ack reg + (n?1) value write value in register reg0 + (n? 1) ack n register read figure 18. write followed by read transaction
NCP81231 www.onsemi.com 20 write in part write operation will be achieved by only one transaction. after the chip address, the mcu first data will be the internal register desired to access, the following data will be the data written in reg, reg + 1, reg + 2, ..., reg +n. from mcu to ncp 81231 start ic address 0 ack register reg 0 address ack stop from ncp 81231 to mcu sets internal register pointer 0 write reg value write value in register reg 0 ack reg + (n? 1) value write value in register reg 0+ (n? 1) ack n register read figure 19. write in n registers
NCP81231 www.onsemi.com 21 package outline qfn32 5x5, 0.5p case 485ce issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 17 32 e2 32x 8 24 l 32x bottom view top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c 25 e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 3.40 3.60 e 5.00 bsc e2 e 0.50 bsc l 0.30 0.50 3.40 3.60 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.70 0.30 3.70 32x 0.62 32x 5.30 5.30 note 3 dimensions: millimeters l1 detail a l alternate constructions l ??? ??? a-b m 0.10 b c m 0.05 c k 0.20 ??? l1 ??? 0.15 pitch recommended on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81231/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

▲Up To Search▲

Price & Availability of NCP81231

	To Download NCP81231 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .